1. Field of the Invention
The present invention relates generally to data access of computer bus, and more particularly, to a collaborative bus arbitration multiplex architecture and a method arbitration of data access based on the architecture.
2. Description of the Related Art
Referring to FIG. 7, a conventional computer includes a bus master peripheral device (BMPD) having the function of bus master for access to the data block of the main memory via direct memory access (DMA) engine and memory description table (MDT).
In the aforesaid architecture, the DMA engine can actively access the data block of the main memory via the bus subject to the MDT. The MDT includes at least one memory descriptor, each of which records the size, location, and other additional information of the data block.
Referring to FIG. 8, alternatively, the MDT can be put into the main memory. In the meantime, in the DMA engine, the MDT can be fetched via the pointer of first table indicative of the location of the MDT. In such architecture, the general main memory includes a paging structure, so the MDT can be one and more, which are connected with each other via a link list (not shown). The DMA engine can fetch the MDTs one by one to access the corresponding data blocks.
Referring to FIG. 9, the general computer system includes at least one BMPD and the bus includes an arbitrator functioning as arbitration. Only one BMPD can have access to the bus within each unit time.
An example of the BMPD having the MDT is taken for illustration hereinafter. Under the normal circumstances, the BMPD can fetch access authority from the arbitrator of the bus according to the MDT thereof to further access the corresponding data block. In FIG. 9, the data block is represented by #m; even if the same data block is accessed, it is still permissible. It indicates that the data is read multiply when the reading action proceeds. When the write-in action proceeds, second write can overwrite first write, so such design is meaningless in practical application.
In each of aforesaid three prior techniques, there is none of any management protocol for multiple BMPDs to access the same data block, so whichever BMPD fetches control authority, its treatment will proceed firstly. However, bandwidth of the main memory will be mostly wasted and the other BMPDs will idle to further waste time.